1. Field of the Invention
The present invention relates to semiconductor device and fabrication methods, and more particularly to a process for fabricating short-channel field effect transistors using relatively large design rule fabrication equipment.
2. Description of the Related Art
It is desirable in the production of large scale integrated circuits, or semiconductor chips, to reduce the size of the individual semiconductor devices comprising the circuitry on the chip. This generally provides for an increase in the number of active devices provided on a single wafer or chip and often also provides for a lower overall power requirement for the chip. Short-channel field effect transistors (FETs), having a channel length in the submicron range (less than one millionth of a meter), are one example of semiconductor devices presently sought to be fabricated with reduced size. However, efforts to produce short-channel FETs have generally made use of lithographic techniques requiring expensive, specialized and/or complicated fabrication equipment or processes.
The processes used in the production of semiconductor devices are relatively detailed, sophisticated, and precise. Generally, a semiconductor designer does not have to deal with or modify the details of these processes directly because a set of design rules is provided corresponding to the particular equipment used during the fabrication process. The design rules and electrical parameters are specified or predetermined by the fabrication process and equipment used to make the chip. The designer lays out the semiconductor device structures and circuitry using the design rules to avoid problems associated with tolerance errors of the fabrication equipment. By following the established design rules, the designer does not have to be concerned with the actual details of the tolerance limits of the particular fabrication equipment.
Because the design rule is predetermined by tolerance limits of the particular fabrication equipment, it is based on a minimum semiconductor feature size producible by the equipment with relative reliability. For example, conventional fabrication of short-channel FETs begins with the formation of the gate polysilicon using a relatively precise lithographic step, which is often relatively unreliable, and which uses expensive equipment and/or complicated techniques to define the small gate length. The source and drain areas of the FET are subsequently formed using a self-align technique in which the respective source/drain areas are aligned with the gate polysilicon.
For example, a conventional process for forming a FET with a 0.5 micron gate length usually employs an optical patterning or photo-reduction technique employing a "step and repeat" procedure to define the submicron gate length. An optical stepper or photo-repeater apparatus is used to create an optical mask for patterning a given material layer of the semiconductor device structure. An optical stepper operates with a wavelength corresponding to a given optical resolution. Two standard wavelengths employed by optical steppers are commonly termed "i-line" or "g-line". To produce a 0.5 micron gate length FET a relatively expensive i-line optical stepper is usually required, or a relatively difficult and involved phase shift mask process is required. Similarly, a process for forming a FET with a gate length approximately below 0.25 micron usually employs x-ray lithographic technology (x-ray lithography) which is very expensive and relatively unreliable.
Accordingly, it would be highly advantageous and desirable to produce reduced size semiconductor devices, including short-channel (submicron) FETs, while using more common, reliable, inexpensive, relatively standard, large design rule semiconductor fabrication equipment available in the industry. In particular it would be desirable to provide for the fabrication of FET devices having a submicron channel or gate length which is well below the design rule tolerance of the fabrication process to used to make the FET.